1. Field of the Invention
The present invention relates to a redundancy circuit of a semiconductor memory device and more particularly to substituting memory cells having defective rows with redundant or spare memory cells.
2. Description of the Related Art
One common technique used to improved the yield of a particular semiconductor memory fabrication process is to "repair" defective memories which result from the fabrication process. Repairing cells increases the percentage of usable memories resulting from the repairs and the original fabrication process. Semiconductor memories are commonly fabricated with redundant memory cells (generally called spare memory cells) to replace defective memory cells within the same memory.
It is known to the public that the redundancy has been proposed to improve the yield of a semiconductor memory device. Here, the term "redundancy" refers to a process for replacing a predetermined memory cell when a defect occurs, therein with redundant memory cells (i.e., commonly designated as spare memory cells). For example, in case of a row redundancy, a row address corresponding to the memory cell with the defect is decoded and used to remedy the defect in the normal memory cell by means of the additional redundant cells. Substituting the redundant row of memory cells for the row with the defect thus "repairs" the memory device.
Generally, as packing density increases the number of the memory cells increase. Recently, memory cells are arranged in a plurality of submemory cell arrays. Usually, a redundant memory cell array is provided within each such submemory cell array, so that when a defective memory cell occurs in one of the submemory cell arrays, the defective memory cell row in the array is repaired by means of the redundant row of memory cells.
In connection with this operation, a block diagram illustrating a memory device using such a conventional repair method is shown in FIG. 1. Here, the memory cell array is formed of four submemory cell arrays MA0, MA1, MA2 and MA3. The submemory cell arrays respectively have row decoders X0, X1, X2 and X3, and spare word lines, which are generally referred as redundant word lines. Also, spare decoders SD0, SD1, SD2 and SD3 are provided for driving the spare word lines during the redundancy operation. The number of the spare decoders SD0, SD1, SD2 and SD3 is the same as the number of the spare word lines within each submemory cell array MA0, MA1, MA2 and MA3. The spare decoders SD0, SD1, SD2 and SD3 receive internal submemory cell array address signal a.sub.0 -a.sub.n-3 and drive the spare word lines by means of their combination rather than the normal word line. Therefore, if the defect occurs in the normal word line of the submemory cell array MA0, for example, the defective word line address is programmed in one of the spare decoders SD0, SD1, SD2 and SD3. Substituting this spare word line for the normal work line thus repairs the submemory array.
However, in the device shown in FIG. 1, four spare word lines are substituted for one defective normal word lines (i.e., the normal word lines without defects are also substituted in each of the submemory arrays). Because the probability of a defect in the spare word lines increases. Moreover, the number spare word lines provided for each submemory cell array is predetermined and not alterable, which leads to an increase in the required chip area.
FIG. 2 shows another example illustrating memory device using another conventional redundancy technique. In the FIG. 2 device, the spare word lines provided one submemory cell array number less than those of FIG. 1, (two rather than four) and a spare decoder for driving each spare word line is provided as shown in the construction of FIG. 2. If one normal word line is defective in a given submemory array, this defective word line is repaired by only one spare word line in that submemory array. Also, each defective normal word line causes substitution of only a single word line. This one-to-one repair method is performed by enabling only the one spare decoder.
The system shown in FIG. 2 thus solves the above-described problems of all the redundant word lines in each submemory array being substituted, but it also has problems. Since the number of the spare word lines provided to one submemory cell array decreases, defect cannot be repaired when the number of the defective normal word lines in a submemory cell array is greater than the number of the spare word lines provided to the submemory cell array. Furthermore, one spare decoder must be provided for each spare word line which increases the required number of the spare decoders. Thus the area occupied by the spare decoders is increased which is not suitable for high packing density.
FIG. 3 shows a memory device using yet another conventional technique to solve the above-described problems. The redundancy shown in FIG. 3 is referred to in Korean Patent Application No. 90-21502 entitled: "Redundancy circuit and Method of a Semiconductor Memory Device" filed by this applicant. The circuit shown in FIG. 3 contains a redundant cell array 14, which is used with two normal memory cell arrays 10 and 13, and an isolation gate 12 is installed between the two normal memory cell arrays 10 and 13. In the redundant operation mode, a redundant sense amplifier 15, connected redundant memory cell array 14, is operated. Thus, regardless of whether the defect occurs in either of the normal memory cell arrays 10 or 13, the defect can be repaired using only by means of one redundant memory cell array 14. Thus, this device desirably decreases the required size and/or increases the packing density. However, in the device shown in FIG. 3, since the spare word line and a redundancy decoder circuit are dependent upon the normal memory cell arrays 10 and 13, word-line failures can only be repaired by the associated redundant memory cell array. Because defects in the memory cells normally do not uniformly appear, but tend to be concentrated in, for instance, a single memory array, the fact that the number of repairable cells is restricted by the number of associated redundant memory cells restricts the improvement of redundancy efficiency. Also, while the layout of the FIG. 3 design obtains a higher packing density than the FIGS. 1 and 2 embodiments, a still higher packing density is needed for current memory device designs.